1. Field of the Invention
The present invention relates to clocked integrated circuits generally, and more particularly to integrated circuits with adjustable delay lines to support timing requirements.
2. Background
A variety of integrated circuits with different mission functions have high clock rates and as a result have precise timing requirements. For example, in some memory devices, the time between applying a read signal in one clock cycle, and sampling in another clock cycle, the data output in response to the read signal must be precisely controlled. However, producing signals with precise delays across a product line is a nontrivial problem due to semiconductor process variations that occur from one wafer to another wafer, from one integrated circuit to another integrated circuit on the same wafer, and even across different portions of the same integrated circuit.
A common approach to addressing process variations is to employ a design methodology with a “worst case” modeling approach. Such an approach consistently underestimates circuit performance, and results in expensive over-design. A needed approach is to make integrated circuits that satisfy demanding timing requirements without unnecessary and expensive over-design.